Decoder
US4247921A · kind A · utility
14Cited by
1References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 1979 |
| Grant date | Jan 27, 1981 |
| Priority date | — |
| Expiry date | Jul 31, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A decoder for decoding address signals and a clock signal, in a synchronous CMOS memory, comprising an MOS transistor of one conductivity-type, to whose gate is applied a clock-including address signal, and a plurality of MOS transistors of the opposite conductivity-type connected in series, to each gate of which is applied the address signal and the clock-including address signal, respectively, whereby a terminal connecting the MOS transistor of one conductivity-type and the MOS transistors of the opposite conductivity-type serves as an output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.