LSI Semiconductor device and fabrication thereof
US4249193A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 1978 |
| Grant date | Feb 3, 1981 |
| Priority date | — |
| Expiry date | May 25, 1998 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/923
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is an improved masterslice design technique including structure, wiring, and method of fabricating, to provide improved Large Scale Integrated Devices. In accordance with the improved masterslice technique a plurality of semiconductor chips are provided wherein essentially the entire semiconductor surface area of each chip is utilized to provide cells selectable to be personalized (wired). None of the semiconductor surface area is dedicated for wiring channels. The individual cell area and cell configuration is optimally arrived at to facilitate wiring the maximum number, if not all of the cells contained on each chip, whereby circuit density is materially improved and a wide variety LSI device part numbers may be readily fabricated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.