Multi function patch pin circuit
US4250407A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 1977 |
| Grant date | Feb 10, 1981 |
| Priority date | — |
| Expiry date | Nov 23, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0823
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A single patch on an integrated circuit is arranged to patch any one of four different logical states into the circuit, according to whether the pin is grounded, floating, coupled to a supply rail via a resistor, or coupled to the supply rail directly. In one embodiment, the voltage thresholds of three transistors are arranged so that they switch on successively in response to successively higher voltages on the patch pin, thereby controlling the binary logic signals at each of two output points in the circuit; in the other embodiment, multi-emitter transistors are arranged with differing current thresholds to achieve the same result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.