Symmetrical memory plane for cross-tie wall memory system
US4250565A · kind A · utility
12Cited by
2References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 23, 1979 |
| Grant date | Feb 10, 1981 |
| Priority date | — |
| Expiry date | Feb 23, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/0858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a cross-tie wall memory system for the generating, propagating and detecting of binary data represented by the presence or absence of cross-tie, Bloch-line pairs along a cross-tie wall in a thin magnetic layer. The system includes a three-level structure comprised of the following superposed layers: a straight-edged current conductive stripline; a serrated-edged thin magnetic layer data track, and a wide-narrow-edged current conductive stripline terminated on one end by a cross-tie, Bloch-line pair generator and on the other end by a cross-tie detector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.