Redundant memory circuit
US4250570A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 1978 |
| Grant date | Feb 10, 1981 |
| Priority date | — |
| Expiry date | Jan 9, 1998 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/781
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A redundant memory circuit for a memory array in which the memory has a preselected number of rows and columns having addresses associated therewith and decoders coupled thereto and one or more redundant rows or columns having initially unspecified addresses associated therewith and redundant decoders coupled thereto. The redundant memory circuit programs the redundant decoders coupled to the redundant rows or columns having initially unspecified addresses to match the addresses of defective rows or columns having addresses associated therewith and disables one or more of the defective rows or columns having addresses associated therewith.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.