Dynamic zero offset compensating circuit for A/D converter
US4251803A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 1978 |
| Grant date | Feb 17, 1981 |
| Priority date | — |
| Expiry date | Jun 2, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1295
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a dynamic compensation circuit for correcting the residual offset voltage encountered in an analog-to-digital conversion chain. Samples of an analog signal having an average value equal to 0 are provided to a first input of a comparator, the second input of which receives a reference signal generated through a D to A converter under control of a control logic circuit. A sample and hold circuit with the comparator causes a DC offset of the output signal level which is to be dynamically corrected by the compensating circuit of the invention. The DC offset causes the duty cycle to differ from one by an amount .DELTA.DC which will be the error curve signal of the compensation circuit. The compensating circuit reduces the .DELTA.DC to 0 by adding to the signal a DC voltage opposite to and of equal magnitude to the offset voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.