Integrated circuit package
US4251852A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 1979 |
| Grant date | Feb 17, 1981 |
| Priority date | — |
| Expiry date | Jun 18, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a packaging structure wherein one or more integrated circuit semiconductor chips are mounted on membrane-like insulating members. The membrane-like members provide multilevel wiring and interconnection between the chip or chips and a secondary wiring structure. The packaging structure includes a module protective cap (preferably metal) and resilient means supported by said secondary wiring structure. The resilient means physically biases the semiconductor chip or chips against the module protective cap and also accommodate induced chip motion and variation. The packaging structure provides enhanced thermal, mechanical and electrical characteristics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.