Memory unit with pipelined cycle of operations
US4253147A · kind A · utility
46Cited by
9References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 9, 1979 |
| Grant date | Feb 24, 1981 |
| Priority date | — |
| Expiry date | Apr 9, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory unit is disclosed for receiving and executing instructions transmitted along buses. The memory unit includes registers and control logic that permit it to accept a second instruction from the bus and begin error checking procedures on the second instruction, all while completing the execution of a first instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.