Silicon barrier Josephson junction configuration
US4253230A · kind A · utility
9Cited by
4References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 9, 1979 |
| Grant date | Mar 3, 1981 |
| Priority date | — |
| Expiry date | Feb 9, 1999 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49014
Abstract
A planar, silicon barrier, Josephson junction and method of forming the jtion which does not require expensive high-resolution, lithography techniques such as electron beam or x-ray. The method includes an etching mask-etch process which forms the basic structure configuration using a (110)-cut silicon wafer. Subsequent to the etching process the mask is removed and a superconducting film is deposited on the previously formed silicon surface to produce a single crystal silicon barrier with good electrical properties.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.