Method of manufacturing solid-state devices in which planar dimensional distortion is reduced
US4256829A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 3, 1978 |
| Grant date | Mar 17, 1981 |
| Priority date | — |
| Expiry date | May 3, 1998 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/948
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of manufacturing a microminiature solid-state device includes first and second exposure steps in which radiation-sensitive material on a solid-state substrate is exposed radiation through a mask pattern to define locations for localized processing. A local processing step between the first and second exposure steps causes an undesired dimensional distortion of the substrate surface in the plane of the substrate surface. This dimensional distortion is then reduced by adjusting the relative sizes of the area of the substrate surface and the area of the mask used in the second exposure step in an substantially uniform manner prior to the second exposure step. By adjusting the relative sizes of the substrate surface and mask areas in such a way as to compensate for the planar dimensional distortion induced in the first exposure step, such dimensional distortion can be substantially reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.