System bus arbitration, circuitry and methodology
US4257095A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 1978 |
| Grant date | Mar 17, 1981 |
| Priority date | — |
| Expiry date | Jun 30, 1998 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Arbitration of a system bus shared by a plurality of digital processors, input and output devices and memories may be shared in an intelligent and efficient manner by using an arbitration method and an arbiter and bus controller circuit which allows a lower priority processor or user to access the system bus during those times in which a higher priority user of the system bus is not actively accessing the system bus. Thus, without altering the priority assignments among multiple users of a system bus, lower priority users requesting access may be allowed selective and limited access to the system bus during those times in which a higher priority user is in either an idle or halt state or is engaged in utilizing another bus, such as an input/output bus or resident bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.