Line hold circuits
US4258232A · kind A · utility
11Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 25, 1979 |
| Grant date | Mar 24, 1981 |
| Priority date | — |
| Expiry date | May 25, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04M1/80
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A single line hold circuit adapted for connection between the tip and ring leads of a telephone line. The circuit comprises impedance means for connection between the tip and ring leads, the impedance means including a semiconductor element having high and low impedance states, the impedance of the low impedance state being sufficiently small to maintain the telephone line in a hold condition. The circuit further comprises means for causing the semiconductor to be in its low impedance state following an interruption of a predetermined length of time in loop current. A double line hold circuit is also illustrated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.