Memory circuit
US4262341A · kind A · utility
8Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 18, 1978 |
| Grant date | Apr 14, 1981 |
| Priority date | — |
| Expiry date | Oct 18, 1998 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is the addition of a capacitor circuit for augumenting the voltages at predetermined points in a sense amplifying circuit, in order to ensure a satisfactory refreshing of memory cells, since, if the potentials at the connecting points between a sense amplifying circuit and bit lines fall below a predetermined value when the sense amplifying circuit is caused to operate, it is difficult to achieve a complete refreshing of the memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.