Fault monitor for numerical control system
US4263647A · kind A · utility
41Cited by
4References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 7, 1979 |
| Grant date | Apr 21, 1981 |
| Priority date | — |
| Expiry date | Feb 7, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05B2219/34466
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Associated with each processor in a multiprocessor numerical control system is a watchdog timer circuit which is periodically reset by its processor under normal operating conditions. If a malfunction should occur in one of the processors, its watchdog timer is not reset and it times out. A fault monitor line connects to each watchdog timer circuit and an emergency stop circuit, and when a malfunction occurs in any one of the processors, this condition is indicated to all the processors and to the emergency stop circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.