Arrangement for extraction and receiving data for a refreshable memory
US4266286A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 8, 1979 |
| Grant date | May 5, 1981 |
| Priority date | — |
| Expiry date | Nov 8, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory of the MOS N channel type comprising two half-memories each conting the same number of columns, each column being bisected at the center by a refreshing amplifier. A bus is alotted to each half-memory and is connectable to any half-column in the half-memory which is addressed so as to read and rewrite in the refreshing phase. The extracting and rewriting arrangement incorporates a flip-flop having its inputs connected to the buses by a differential circuit and its outputs connected to inputs of a read and rewrite circuit. The buses are initialized at a low potential and a reference potential is applied to one bus when the other bus is connected to a half-column. Transient interference rise on the selected bus above the disturbance threshold of the refreshing amplifier is prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.