Low power consumption integrated circuit for a combined timepiece and calculator
US4267577A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 1979 |
| Grant date | May 12, 1981 |
| Priority date | — |
| Expiry date | Apr 26, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3228
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device having a combined time-keeping mode and calculator mode comprises a generator stage for generating basic clock signals and system clock signals, a processor stage responsive to a supply of the system clock signals for executing arithmetic operations required for the timekeeping mode and the calculator mode key input members for introducing information into the processor stage as key input signals, and a clock control for controlling the supply of the system clock signals. The processor stage is adapted to develop a command signal to indicate the completion of the arithmetic operations. The clock control is responsive to the rising and trailing edges of the key input signals for enabling the supply of the system clock signals. The generation of the command signal causes the clock control to prevent the system clock signals from being fed to the processor stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.