Memory address designating system
US4267581A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1979 |
| Grant date | May 12, 1981 |
| Priority date | — |
| Expiry date | Mar 5, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/321
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory address designating system comprising a program counter and data counter for holding the addresses of an instruction word area and data area respectively of a memory, an increment/decrement counter for modifying the address, and gate circuits for controlling data transfer between the program counter, data counter and increment/decrement counter, in which, when the memory is accessed by the addresses of the instruction word area and data area of the memory, an address held in the program counter is modified by an increment/decrement counter and consequently is incremented by one and sent through a gate to the data counter where it is held. On the other hand, the address of the data area held in the data counter is supplied through a gate to he program counter and then to the increment/decrement counter where it is modified. At the same time, the data of the data area of the memory is fetched and the modified address is supplied to the data counter while the modified address stored in the data counter is supplied to the program counter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.