Acquisition delay circuit for a PLL reference oscillator
US4267602A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 1979 |
| Grant date | May 12, 1981 |
| Priority date | — |
| Expiry date | Oct 4, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay circuit for enhancing acquisition of a synthesizer PLL subsequent to change in the synthesizer's frequency of operation or a change in the source of tuning voltage applied to a voltage-controllable reference oscillator. A control circuit determines whether the reference oscillator operates in a crystal-controlled or in a voltage-controlled mode. The delay circuit includes a monostable having an output coupled to the control circuit and a trigger input coupled to both an ENTER CHANNEL indicator and a pulse generator. The monostable is triggered, thereby assuring temporary crystal-controlled operation of the reference oscillator, in response to an ENTER CHANNEL indicator or to an output from a pulse generator. The pulse generator is responsive to a change in the source of reference oscillator tuning control voltage from, for example, a manually variable fine tuning potentiometer to an AFC control circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.