Timing adjustment circuit for digital switching
US4270203A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1978 |
| Grant date | May 26, 1981 |
| Priority date | — |
| Expiry date | Nov 13, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/07
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A slip-free timing adjustment system adjusts channel timing for a multiplexed digital data stream. The data stream in each of c time division channels (10, 11) is modified preparatory to switching in a digital time-division circuit switch (14). The multiplexed digital data stream may arrive at the switch at a rate R0. The switch clock rate may be at a rate R1. Rates R0 and R1 are potentially different. Signal means (12, 13) provide for inserting a variable length timing code, one bit at a time, in each of the c channels in each multiplexed digital data stream. The multibit timing code is composed of successive variable length code words of length L and L+1 bits. Adjustment means (18, 42) receives the multiplexed data stream and adjusts individual channel rates in each of the c channels. This includes means for altering the length of the variable length code words by adjusting code words of length L to code words of length L+1 when the input clock is slower than the switch clock and for adjusting code words of length L+1 equal to code words of length L when the input clock is faster than the switch clock. By this means, the respective clock rates are equalized by the adjustment of j…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.