Delay circuits
US4271483A · kind A · utility
5Cited by
3References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 1978 |
| Grant date | Jun 2, 1981 |
| Priority date | — |
| Expiry date | Jul 31, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/0026
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Digital delay apparatus for variable delay uses a shift register fixed delay driving a random access memory variable delay. A variable modulus counter controls the read-write addressing, whereby the difference between addresses sets the variable delay of the random access memory. The random access memory capacity is small relative to the shift register for increased efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.