Supervisory signaling for digital channel banks
US4271509A · kind A · utility
11Cited by
5References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 13, 1979 |
| Grant date | Jun 2, 1981 |
| Priority date | — |
| Expiry date | Jul 13, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/12
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A digital transmission system is disclosed in which time slots in selected frames are reserved for supervisory signaling bits. These signaling bits can be used to represent a large number of supervisory states by assigning at least three bit patterns to each of two interleaved streams of supervisory bits. These bit patterns may include, for example, continuous ones, continuous zeros and alternating ones and zeros. A supervisory state encoder and decoder for these bit patterns are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.