Integrated circuit with I.sup.2 L and power transistors and method for making
US4272307A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 12, 1979 |
| Grant date | Jun 9, 1981 |
| Priority date | — |
| Expiry date | Mar 12, 1999 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/088
Abstract
An integrated circuit has a P-type substrate and two N-type epitaxial layers. P-type isolation walls define pockets in the dual-layer epitaxial material, a power transistor being formed in one and an inverted I.sup.2 L transistor being formed in another of the pockets. An upper buried layer doped with antimony (N-type) at the interface between the two epitaxial layers extends into the outer epitaxial layer forming a N.sup.+ N holes-barrier junction. This junction is spaced from the depletion region of the normally forward biased base emitter junction by from 0.1 to 0.45 holes-diffusion lengths to provide high emitter efficiency in 0.5 to 5 ohm-cm epitaxial material. The P-type bases of the two kinds of transistors have the same depth but the N-type emitter of the power transistor is shallower than the N-type collector of the inverted transistor although formed earlier. Breakdown voltage of the power transistor is thus enhanced while the base width of the I.sup.2 L transistor is predictable and uniform being substantially determined by late and independent process steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.