Output capacitor discharge circuit
US4272717A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 12, 1979 |
| Grant date | Jun 9, 1981 |
| Priority date | — |
| Expiry date | Mar 12, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H3/243
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
In accordance with this invention, the capacitor is discharged through a transistor connected as a negative resistance device so that the current through it increases as the voltage across the capacitor decreases. Means are provided for biasing the transistor to cut-off while the output voltage is being regulated at the selected value, but the bias is removed so as to permit the transistor to conduct and discharge the capacitor under certain conditions, such as (1) when the voltage is programmed downward; (2) when an overvoltage condition exists; or (3) when the line voltage to which the power supply is connected fails or is turned off. In the latter situation, a capacitor supplies operating power to the circuit for a long enough time to permit it to fully discharge the capacitor. In accordance with another aspect of the invention, the time during which the transistor is permitted to conduct is limited so as to permit more current to flow without damaging the transistor and thereby discharge the capacitor more quickly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.