Data line potential setting circuit and MIS memory circuit using the same
US4272834A · kind A · utility
13Cited by
1References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 3, 1979 |
| Grant date | Jun 9, 1981 |
| Priority date | — |
| Expiry date | Oct 3, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A potential setting circuit is connected with a pair of common data lines which are made operative to receive data signals from memory cells. The potentials at the paired common data lines, which are forcibly set by the potential setting circuit, are set substantially at the middle level between the high and low levels of the data signals which are generated from the memory cells. As a result, the potential at the paired common data lines are changed within a relatively short time to the level of the data signals generated from the memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.