MOS decoder logic circuit having reduced power consumption
US4275312A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 1978 |
| Grant date | Jun 23, 1981 |
| Priority date | — |
| Expiry date | Nov 30, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/005
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a transistor circuit, and more specifically to a static decoder circuit made up of a series circuit of a NOR logic gate circuit consisting of a plurality of MISFET's for receiving address signals through the gates, an inverter circuit for receiving the output of the logic gate circuit through the gate, a first MISFET for receiving the output of the logic gate circuit through the gate, and a second MISFET for receiving the output of the inverter circuit through the gate, wherein said NOR logic gate circuit and inverter circuit are connected to a ground terminal via a first switching MISFET which receives the control signals through the gate, and said series circuit is connected to a power supply terminal via a second switching MISFET which receives the control signals through the gate. According to the circuit of the present invention, said first and second switching MISFET's are rendered off by said control signals during the standby periods, such that the current pass is completely interrupted between the power supply terminal and the ground terminal in the decoder circuit, and the output of the decoder circuit is rendered to acquire the ground lev…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.