FET driver circuit with short switching times

US4276487A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Luis M. Arzubi · Eppelheim, DE
• Rainer Clemen · Böblingen, DE
• Jorg Gschwendtner · Eßlingen, DE

Key dates

• Filing date: Apr 4, 1979
• Grant date: Jun 30, 1981
• Expiry date: Apr 4, 1999

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K19/018557
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A field effect transistor driver circuit responsive to a single input pusle generates a highly loadable output clock pulse with short rise and fall times, the rising edge being shifted relative to said input pulse by a controllable delay time but the trailing edge remaining practically undelayed. This advantageous pulse form is achieved through an improved controlling of a bootstrap output stage. Two preceding stages, i.e., a transmission gate and a delay stage supply two out-of-phase control pulses with high amplitudes and steep edges. Of essential importance is the novel delay stage which is designed as push-pull stage with a load FET and a driver FET. The gate of the load FET is controlled by the output pulse of the bootstrap stage 2 fed back via a third FET and by a capacitively coupled-in input pulse at the drain, whereas the gate of driver FET is controlled from the bootstrapped output of the transmission gate. The connecting point of load and driver FET represents the output of the delay stage. For the quick switching-on and delayed but speedy switching-off of the driver FET's of the bootstrap output stage a pulse equal in amplitude to the input pulse is generated. That puls…