Instruction pre-fetch microprocessor interrupt system
US4279016A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 1979 |
| Grant date | Jul 14, 1981 |
| Priority date | — |
| Expiry date | Jun 21, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interrupt system for an instruction pre-fetch microprocessor is provided. The interrupt system includes an instruction address register coupled to a storage address register for holding the next succeeding instruction address to the pre-fetched in a sequence of instructions. A storage address register is provided and is coupled to the instruction address register and is coupled to the storage address register for holding the storage address to be accessed. A first latch receives and stores an interrupt request from one of a plurality of peripheral devices. A second latch, enabling interrupts, is coupled to the storage unit and controlled by instructions from the microprocessor. An interrupt link register stores values of the instruction address register and page information together with arithmetic and logic unit status bits when an interrupt request has occurred from one of the plurality of peripheral devices and an interrupt cycle is executed. The system further includes an interrupt circuit coupled to the first and second latches for inhibiting updating of the instruction address register to a next succeeding instruction. Circuitry is coupled to the first and second latches f…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.