Method for qualifying biased burn-in integrated circuits on a wafer level
US4281449A · kind A · utility
71Cited by
7References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 21, 1979 |
| Grant date | Aug 4, 1981 |
| Priority date | — |
| Expiry date | Dec 21, 1999 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49004
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Integrated circuits in dice on a wafer are biased burn-in qualified by providing two sets of conductors connected to each die by fusible elements, biasing the dice using said conductors during the high temperature burn-in, testing the fusible elements, removing the conductors, and testing the circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.