Gated oscillator
US4286233A · kind A · utility
3Cited by
7References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 9, 1979 |
| Grant date | Aug 25, 1981 |
| Priority date | — |
| Expiry date | Jul 9, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/03
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A gated oscillator implemented with cascade-connected inverting logic circuits and resistor-capacitor timing elements generates oscillations so long as an inhibiting signal is not applied to one of the logic circuits. Means are provided to maintain potentials on the timing elements during application of inhibiting signal, which potentials are equivalent to steady-state operating potentials at the inception of a state transition. When the inhibiting signal is discontinued allowing oscillations to be generated, the initial pulse period is equal to the steady-state pulse period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.