Common bus communication system in which the width of the address field is greater than the number of lines on the bus
US4286321A · kind A · utility
75Cited by
4References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 18, 1979 |
| Grant date | Aug 25, 1981 |
| Priority date | — |
| Expiry date | Jun 18, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0623
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The technique for transmitting address information between a processor and a plurality of memory subsystems in a common bus communication system. The width of the address field is greater than the number of lines on the bus. For example, addresses are three bytes wide, and the bus is one byte wide, thereby reducing the number of pins required on the processor and the subsystems. For communication between the processor and a given memory subsystem, only those bytes of a selected address which differ from the corresponding bytes of a previous address are transmitted sequentially for accessing a selected memory location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.