Edge sense latch
US4287442A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 1979 |
| Grant date | Sep 1, 1981 |
| Priority date | — |
| Expiry date | Feb 26, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356017
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An MOS logic circuit is provided which generates and latches an output signal at a given logic level upon detection of a given transition in an input signal coinciding with a given state of a clock signal. The circuit utilizes the capacitance inherent in an MOS structure. The circuit requires a minimum of MOS components and is therefore useful in high density MOS integrated circuits where it is desired to detect and latch a transition in a signal. The edge sense latch comprises an MOS inverter (Q1, Q2) responsive to an input signal S, a transmission gate (Q3) controlled by a clock signal, a transmission gate (Q4) controlled in part by an inherent capacitance (29), a latch comprising a pair of cross-coupled MOS transistors (Q5, Q8) for generating an output signal Q, and an MOS transistor (Q6) responsive to a reset signal R.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.