Topography for integrated circuit pattern recognition array
US4287507A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 1979 |
| Grant date | Sep 1, 1981 |
| Priority date | — |
| Expiry date | May 30, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit for sequentially receiving a plurality of binary interval numbers, each representing the width of a time interval occurring during optical scanning of a bar coded label, includes first, second, third and fourth sequentially located edges forming a rectangle. The integrated circuit includes input logic circuitry for receiving and temporarily storing the binary interval numbers and a plurality of adders and shift registers for adding predetermined ones of the stored binary interval numbers and storing the resulting sums. The integrated circuit includes a plurality of comparators for comparing predetermined ones of the sums and stored sums to produce a plurality of intermediate signals. Encoding circuitry encodes predetermined ones of the intermediate logic signals to produce a digital character number representing a character scanned on the bar coded label and also includes output circuitry. The input logic circuitry is located adjacent to the first edge, and the plurality of comparator circuits are located generally along the third edge. The shift register and adder circuitry is generally located between the input logic circuitry and the plurality of comparator…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.