Method for qualifying biased integrated circuits on a wafer level
US4288911A · kind A · utility
28Cited by
8References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 21, 1979 |
| Grant date | Sep 15, 1981 |
| Priority date | — |
| Expiry date | Dec 21, 1999 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/953
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Integrated circuits in dice on a wafer are qualified by providing two sets of conductors connected to each die by fusible elements, biasing the dice using said conductors during exposure to a qualifying environment, testing the fusible elements, removing the conductors and testing the circuits. Where the environment is gamma radiation, the fusible elements are tested before annealing of radiation damage and the circuits are tested before and after annealing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.