Computer system having a paging apparatus for mapping virtual addresses to real addresses for a memory of a multiline communications controller
US4290104A · kind A · utility
15Cited by
10References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 2, 1979 |
| Grant date | Sep 15, 1981 |
| Priority date | — |
| Expiry date | Jan 2, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A paging apparatus includes addressing hardware for addressing a number of physical devices coupled to various communication buses, for mapping virtual addresses to real addresses, and controlling the flow of data. The paging apparatus generates 8 control signals, 5 of which modify a virtual address into a real address of a memory thereby expanding the capabilities of the real address from 256 address locations by an additional 512 address locations. The remaining 3 control signals control the flow of data by enabling or disabling data control apparatus in the physical devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.