Decibel addition circuit
US4290111A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 12, 1979 |
| Grant date | Sep 15, 1981 |
| Priority date | — |
| Expiry date | Dec 12, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/0307
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An addition circuit for adding two decibel measurements received at input terminals 12 and 14, first substracts the inputs in a subtractor circuit 16 to obtain a difference d. Then, based upon the magnitude of the difference d, the addition circuit determines the value of 10 log [1+10.sup.d/10 ] or 20 log [1+10.sup.d/20 ] in a read-only memory circuit 20. A selector circuit 24 determines which of the two input decibel measurements is the larger and controls the complementer circuit 18 so that the value of the difference d is always negative. The output of the read-only memory circuit 20 is added to the larger of the two input in an adder 22.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.