Memory device protected against undesirable supply voltage level
US4290119A · kind A · utility
13Cited by
2References
9Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Feb 7, 1980 |
| Grant date | Sep 15, 1981 |
| Priority date | — |
| Expiry date | Feb 7, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes memory cells and access circuit for accessing to desired memory cells. The access circuit is driven by a driver which includes an emitter coupled logic for providing a switch-on signal of a low level in response to an input signal. A switch circuit in the driver provides the access circuit with a drive signal of a low level in response to the switch on signal. The driver further includes a control circuit for clamping the output of the emitter coupled logic to a non-drive signal of a high level when supply voltages does not satisfy predetermined conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.