Method of making integrated semiconductor structure having an MOS and a capacitor device
US4290186A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 1979 |
| Grant date | Sep 22, 1981 |
| Priority date | — |
| Expiry date | Jul 23, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/66
Abstract
This disclosure is directed to an improved semiconductor capacitor structure especially useful in an integrated semiconductor structure with an MOS device and fabrication methods therefor. This semiconductor capacitor is particularly useful for forming the capacitor portion of a single MOS memory cell structure in a dynamic MOS random access memory which utilizes one MOS device in combination with a capacitor. In one specific disclosure embodiment, the semiconductor capacitor comprises a boron (P) implanted region in a substrate of P- type conductivity followed by a shallow arsenic (N) implant into the boron implanted region. The boron implanted region provides a P type conductivity which has a higher concentration of P type impurities than the concentration of impurities contained in the substrate which is of P- type conductivity. Thus, the boron implanted region performs the important function of preventing a surface N type inversion layer from being formed across the semiconductor surface beneath the silicon dioxide insulating layer which could occur across the substrate P- surface if the arsenic implant region was made into the P- substrate without the P type boron implant. The…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.