Driver circuit for use in an output buffer
US4291242A · kind A · utility
21Cited by
7References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 21, 1979 |
| Grant date | Sep 22, 1981 |
| Priority date | — |
| Expiry date | May 21, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01735
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high speed, low power clocked driver circuit is provided. DC paths from voltage V.sub.DD to ground is eliminated by carefully clocking field effect transistors within the driver circuit. By using bootstrapping techniques, the output of the circuit approaches V.sub.DD. Two of the high speed, low power driver circuits are combined to drive a ratioless output circuit in order to provide an output buffer circuit having a TTL compatible output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.