Multistage logic circuit arrangement
US4291247A · kind A · utility
11Cited by
11References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 21, 1979 |
| Grant date | Sep 22, 1981 |
| Priority date | — |
| Expiry date | Sep 21, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Logic circuits, particularly of the integrated semiconductor type, are accessed at improved speeds by preventing pull-ups from occurring during the access time and by the inclusion of on-chip delay circuitry to avoid switching later stages in a manner to lose information while output nodes of earlier stages are high. All stages are activated in response to a single clock pulse edge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.