Taper isolated random access memory array and method of operating
US4291391A · kind A · utility
41Cited by
4References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 14, 1979 |
| Grant date | Sep 22, 1981 |
| Priority date | — |
| Expiry date | Sep 14, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is embodied in a method of operating a dynamic random access memory (RAM) array having individual depletion mode metal-oxide-semiconductor (MOS) transistors as the memory cells. The cells can be programmed to two threshold states providing constant current sensing. Cell programming is by application of appropriate signals to the transistor gate electrode and source. Reading is accomplished by grounding the source and sensing current through the transistor. An intermediate voltage on the gate electrode prevents changes in the state of the cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.