Five device merged transistor RAM cell
US4292675A · kind A · utility
2Cited by
4References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 30, 1979 |
| Grant date | Sep 29, 1981 |
| Priority date | — |
| Expiry date | Jul 30, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4113
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A five device RAM cell comprising a four device Merged Transistor Logic (MTL) cell plus a separate sense line and a fifth bipolar transistor device having a collector connected to one node of the cell, a base connected to the other node of the cell, and an emitter connected to the sense line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.