Method of fabricating mesa bipolar memory cell utilizing epitaxial deposition, substrate removal and special metallization
US4292730A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 12, 1980 |
| Grant date | Oct 6, 1981 |
| Priority date | — |
| Expiry date | Mar 12, 2000 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/977
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory cell having two mesa bipolar transistors separated by a valley in which two doped polycrystalline load resistors are formed. Doped polycrystalline conductors connect the resistors to a respective backside metallic collector contact which is between a support structure and a transistor and to a respective base. The cell is fabricated by removing a substrate upon which was formed an epitaxial layer and top support, applying a backside metallic layer, forming a bottom support, removing the top support, etching the epitaxial layer to form mesas, etching the backside metal to form discrete contacts, and forming multi-level resistors and conductors in the valley between the mesa transistors separated by insulative material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.