Reconfigurable key-in-storage means for protecting interleaved main storage
US4293910A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 1979 |
| Grant date | Oct 6, 1981 |
| Priority date | — |
| Expiry date | Jul 2, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1466
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosure provides a storage protection (SP) array in each of two system controllers (SCs) in a multiprocessing system which has a shared main storage containing a plurality of basic storage modules (BSMs). The BSMs may be operated with block and page interleaved addresses. Each block in main storage is assigned a key-in-storage having an entry in one of the two arrays. A cross-interrogate (XI) bus connects between the SCs. Using the XI bus, each processor request is sent to an SP address register in every SP array. Each array is divided into a plurality of equal groups. Each group has a range identifier register and a comparator. The range identifier register is loaded with a value which controls the range of main storage addresses to which the group is assigned. All of the comparators in each array are connected to a high-order part of the SP address register for the array. The range identifier registers in all of the groups in both arrays are assigned different values which cover the entire address range of main storage, and only one array need contain a particular key-in-storage. A BSM bit and a page bit in the processor request address are put into the high-order field of…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.