Power supply system for monolithic cells
US4295210A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 1979 |
| Grant date | Oct 13, 1981 |
| Priority date | — |
| Expiry date | Sep 4, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4116
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power-supply system for use in a monolithic memory characterized in that the power dissipation of the memory is reduced. Each word line is connected to a current switch circuit comprised of a first transistor the collector of which is connected to a voltage V1, its base being connected to the output of the address decoder, a second transistor the collector of which is connected to a voltage V2. V3 being the second voltage impressed on the memory cells (where .vertline.V2.vertline. is larger in magnitude than .vertline.V1.vertline. and .vertline.V3.vertline. is larger in magnitude than .vertline.V2.vertline.). The emitters are connected to each other and to the corresponding word line. According to the state of the decoder output, the first or the second transistor is conducting, whereby the selected cells are subjected to a voltage having a magnitude of .vertline.V3-V1.vertline. and the non-selected cells are subjected to a voltage having a magnitude of .vertline.V3-V2.vertline..
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.