Power on and low voltage reset circuit
US4296338A · kind A · utility
23Cited by
11References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 1, 1979 |
| Grant date | Oct 20, 1981 |
| Priority date | — |
| Expiry date | May 1, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/223
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An NMOS power on/low voltage reset circuit provides a substantially instantaneous reset enabling signal when a predetermined fraction of the power supply voltage falls below a predetermined reference voltage. In addition, an external capacitor is discharged. A second reset enabling signal is extended until the capacitor is again charged to a predetermined voltage thus allowing the clock oscillators of a microcomputer sufficient time to stabilize. Self test means are also provided. The reset circuit is implemented on the microcomputer chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.