VMOS Transistor and method of fabrication
US4296429A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 26, 1979 |
| Grant date | Oct 20, 1981 |
| Priority date | — |
| Expiry date | Nov 26, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A vertical insulated gate field effect transistor having a first conductivity layer, a second conductivity layer thereon, a third first conductivity layer thereon, a groove extending from the surface of the third layer through the second layer into the first layer, a layer of insulation and gate material in the groove and a shallow first conductivity vertical region extending from the third layer into the second layer along the groove to form a short channel in the second layer with a shallow device junction. The device is fabricated by masking the three semiconductor layers and etching the third layer and part of the second layer to form a groove, diffusing second conductivity impurities to a shallow depth in the groove, continuing the etching to extend the groove through the second layer into the first layer. A layer of insulation and gate material are formed in the groove to produce the vertical channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.