Semiconductor device with double moat and double channel stoppers
US4298881A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 1980 |
| Grant date | Nov 3, 1981 |
| Priority date | — |
| Expiry date | Apr 7, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This invention concerns a so-called double-moat uni-surface type semiconductor device in which two concentric moats are provided in one main surface of the substrate and the edges of the two pn-junctions for blocking main circuit voltages applied to the device are exposed in the surfaces of the moats. Semiconductor layers having high impurity concentrations and serving as channel stoppers are formed on the semiconductor layers exposed in the one main surface of the substrate, contiguous to the moats and spaced apart from the pn-junctions, each high impurity concentration layer having the same conductivity type as the semiconductor layer on which it is formed. The moats are filled with surface passivating material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.