Programmable memory protection logic for microprocessor systems
US4298934A · kind A · utility
22Cited by
3References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 10, 1979 |
| Grant date | Nov 3, 1981 |
| Priority date | — |
| Expiry date | Aug 10, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor system incorporates a buffer limit address register for identifying a memory area to be protected in a microprocessor system, and an address error recognition device responsive thereto for controlling the suppression of a memory write signal in recognition of an address error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.