Semiconductor device gate-drain configuration

US4300148A · kind A · utility

Assignee

• Bell Telephone Laboratories, Inc. · US

Inventors

• William C. Niehaus · New Providence, US
• Stuart H. Wemple · Madison, US

Key dates

• Filing date: Aug 10, 1979
• Grant date: Nov 10, 1981
• Expiry date: Aug 10, 1999

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/877

Abstract

Power handling capability and gain of metal-semiconductor field effect devices is adversely affected by a phenomenon variously known as gate-drain avalanche or gate breakdown which occurs at elevated gate-drain voltage. Consequently, it is desirable to design devices so as to maximize gate-drain breakdown voltage V.sub.gd consistent with maximum output power capability. According to the invention, such voltage is maximized by a gate-drain configuration which involves approximate equalization of per-unit-area mobile charge in a portion of the active layer under the gate contact and in an adjoining portion between gate and drain contacts. Equalization of charge may be achieved by appropriate doping or appropriate choice of layer thickness, either alone or in combination. In particular, if dopant concentration per unit volume is essentially equal in the two portions, approximate equalization of conducting channel thickness in the two portions is called for. Devices of the invention are capable of higher gain and output power as is desirable in applications such as, e.g., the amplification of microwaves.