Data processing system having data multiplex control apparatus
US4300193A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 1979 |
| Grant date | Nov 10, 1981 |
| Priority date | — |
| Expiry date | Jan 31, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/282
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of information, blocks of information may be transferred between main memory and an input/output controller (IOC) synchronously with operations of the central processor unit (CPU). Logic is provided for enabling one unit of the block of information to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and provides the CPU with a channel number assigned to the requesting IOC. Means are provided within the CPU for determining: the direction of the data transfer, the address of the location of the unit of data to be transferred to/from the main memory, and the number of units of data remaining to be transferred between the main memory and the IOC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.